Analog Port

Job Description:
As a member of our dynamic group, you will have the opportunity in Architecture, Design, and Developing Serdes/DDR/PCS/USB/UCIe RTL for low power and advanced mixed-signal circuit macros to be used in various products from high-performance data centers to low power consumer SoCs. A candidate with experience in one or more of the Design fields below is preferred.

Key Qualifications:
• Good understanding of mixed signal concepts
• Good knowledge of RTL digital design fundamentals
• Deep knowledge of Verilog and System-Verilog
• Good understanding of front-end tools (Verilog simulators, linters, clock-domain crossing checkers)
• Working knowledge of synthesis, static timing, DFT is a huge plus
• Good knowledge of scripting languages, Perl, and Python is a plus
• Good knowledge of Firmware, calibration, and adaptation Algorithm developments
• Strong communication and presentation skills and 3+ years of DDR/PCIe/SERDES and supported protocols knowledge is a plus
• Expertise in multi protocols and PCS architecture such as PCIe, SATA, SAS, Ethernet
• Experience in PHY-level protocol test suite development and integration with link layer controllers is a plus
• Ability and desire to lead a team while providing technical guidance

Detailed Description:
In this job, you will be responsible for specifying and/or micro-architecting digital blocks in advanced mixed-signal circuits. You will also be responsible for RTL coding of blocks specified by you or others. Develop micro-architecture and test-chip/test-system specifications. Work closely with the Controller and PCS design team. Document the design for internal and external purposes, including maintaining PHY user guides. Interface with customers and assist in integrating the IP. Participate in all test chip and bring-up activities. Help improve RTL design methodology. Schedule and track the RTL development process. Provide regular status updates.

Education & Experience:
BSEE or MSEE Degree in a technical discipline plus a minimum of 3 years of digital design in the relevant field.

Job Description:
This position is part of a highly skilled multi-geographical team tasked with the development of high-speed DDR and SerDes utilizing the most advanced 7nm, 5nm, and 3nm CMOS technology. You oversee a core part of the high-speed PHY, including GDDR, PCIe, Ethernet, and USB, in advanced FinFet technology nodes used in a key part of High-Performance Computing and Hyper-Scale Data Center markets. A strong understanding of analog/mixed-signal circuit theories, and expert hands-on design skills, are keys to a successful candidate for this position. Each member of the team is expected to be committed to the team's success, drive to best-in-class designs, and ensure customer usage satisfaction with first time right quality mindset.

Key Requirements:
• Strong understanding of analog/mixed-signal design theories and practical concepts such as mismatch, ratio-metric, linearity, stability, noise, and low-power
• Strong understanding of one of the following core components of a high-speed PHY: CDR, PLL, PI, CTLE, TX Driver, Serializer/De-Serializer
• Experience in circuit tradeoff analysis and ability to comprehend system-level specs and their impacts on circuit design, knowledge of PAM4 systems is a plus.
• Understanding of the physical layout requirements and hands-on ability to perform critical layouts, experience in FinFet a plus.
• Proven track record of successful tape out and silicon meeting performance and power specifications, and experience in chip debug/validation/characterization.
• The ability to communicate technical issues and present technical reviews coherently and logically are essential.
• Developing circuit schematics, performing detailed layout reviews, and performing all necessary verification/simulations.
• Optimizing circuits in high-speed paths of the DDR and SerDes for low jitter and low power.
• Conducting design reviews and creating slides and other associated documentation.
• Providing guidance to validation engineers in initial bring-up, debug, and characterization of chips using SerDes IP.

Responsibilities:
Design, pre layout, and post layout verification of circuits used as part of state-of-the-art integrated NRZ and PAM4 GDDR/SerDes, including:
• Rx Continuous-Time Linear Equalizers
• Feed Forward Equalizers
• Decision-Feedback Equalizers
• High-Speed ADCs and DACs
• PLLs, VCOs
• Clock and data recovery circuits
• High-speed clock distribution networks
• TX drivers and serializers

Education:
Bachelor’s or a master’s degree in electrical engineering and 5+ years of related experience.

Job Description:
As an AMS Verification Candidate, you will be involved in Analog and Mixed Signal Verification for high-speed Analog circuits.

Requirements:
• System Verilog, Verilog RTL, Verilog AMS, and Verilog A.
• Developing behavioral models for Mixed Signal Systems
• Familiarity with the Cadence Analog Design Environment (ADE-L/ADEXL/ Maestro), ideally using the AMS simulator.
• Cadence Virtuoso, Spectre circuit simulator, Incisive and AMS simulators experience.
• An understanding of Analog circuit design, transient, DC, AC simulation and Monte Carlo analysis basics.
• Basic understanding of Analog circuits e.g., voltage references, current references, LDOs, PLLs, Bandgap, OPAMP.

Experience:
• Minimum of 5 years experience within a similar role.
• Candidate must have good communication skills along with the ability to work well in cross-disciplinary teams.
• Strong problem-solving ability and being able to leverage existing knowledge effectively and learn new tools/techniques is essential.

Position Overview:
We are seeking a highly motivated Senior CAD Support and Development Engineer to join our dynamic team. With over 3+ years of hands-on experience, you will be a key contributor in driving innovation, optimizing CAD workflows, and providing expert support for CAD software solutions. This role offers the opportunity to work on cutting-edge design projects, mentor junior team members, and implement advanced algorithms and automation tools to elevate design efficiency.

Key Responsibilities:
CAD Development:
• Collaborate with cross-functional design teams to analyze and optimize CAD workflows, ensuring seamless integration into existing processes.
• Develop high-performance custom scripts and automation flows for streamlining repetitive tasks in ECAD workflows.
• Create, test, and implement algorithms to support advanced design, layout, and verification requirements.
• Provide high performance, end-to-end design solutions tailored to the needs of layout, verification, and verification teams.
• Be a part of the advanced tool development team aiming to reduce the analog design time.
• Implement AI/ML algorithms to assist in design optimization when necessary.
CAD Support:
• Deliver advanced technical support for CAD software, including installation, configuration, debugging, and issue resolution.
• Act as the go-to expert for resolving complex CAD-related challenges and software bugs.
• Monitor industry trends, evaluate emerging CAD tools, and recommend updates or enhancements to maintain a competitive edge.
• Ensure CAD systems comply with organizational IT policies, security standards, and licensing requirements.
Training and Mentorship:
• Mentor junior engineers and provide training on CAD workflows, software best practices, and troubleshooting techniques.
• Develop user-friendly documentation, training materials, and knowledge bases to support team learning and development.
• Drive adoption of CAD automation techniques and tools across the organization.

Qualifications and Skills:
• Educational Background: Bachelor’s or Master’s degree in Information Technology, Computer Science, Electrical/Electronics Engineering, or a related field.
• Experience: 3+ years of hands-on experience in CAD software support, customization and development with a proven track record in automating and optimizing CAD workflows for design and verification.
• Programming Expertise: Proficiency in Python, C, C++, Tcl, Perl, or other scripting/programming languages for CAD tool development and automation. Experience with SPICE, SKILL, or similar programming languages is beneficial.
• Tools Proficiency: In-depth expertise in industry-standard EDA tools such as Cadence, Synopsys, Mentor Graphics (Siemens), Altium, and other ECAD platforms.
• Technical Skills: Strong analytical and problem-solving skills, with the ability to troubleshoot under pressure. Knowledge of AI/ML concepts and their application in CAD development is an advantage.
• Soft Skills: Excellent communication and interpersonal skills, with the ability to explain technical concepts to non-technical stakeholders. Proactive, self-driven, and collaborative mindset with a strong commitment to teamwork.

At Analog Port, we’re at the heart of the innovations that shape the way we work, play, and interact with the world. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design. If you share our passion for innovation, we want to meet you.

We're looking for a Design Verification Engineer to join our Hyderabad/Bangalore team. Does this sound like a good role for you?

Key Qualifications:
• Be a technical contributor in the Verification Tasks – Verilog coding of test-benches, System Verilog, SV Assertions, Test cases, data checks, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM, etc.
• Develop block level test bench to speed up IP verification
• Work with the verification team to debug and fix RTL issues
• Should be able to mentor and technically lead a team of engineers

Preferred Experience:
• Typically requires a minimum of 5-10 years of SOC/IP Verification experience
• Able to create test-plan & coverage plan with the specification provided
• Knowledge in Serdes and interface technologies such as DDR, MIPI, PCIe, CXL, USB, Ethernet is a plus
• Knowledge in PHY Verification is a plus
• Able to analyze the coverage metrics and improve them with the help of additional test cases in directed environment, at least for small/medium complexity features of the protocol/product specs
• Familiarity with scripting languages such as shell, Perl, Python etc. is highly desirable
• Experience in GLS verification & Power-aware simulation is a plus
• Experience with Perforce, Git or similar revision control environment
• Deliver assigned task with quality with minimal supervision
• Has strong desire to learn and explore new technologies
• Demonstrates good analysis and problem-solving skills

In addition, the candidate should have good communication skills, should be a team player and possess good problem-solving skills and show high levels of initiative.

At Analog Port, we’re at the heart of the innovations that shape the way we work, play, and interact with the world. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design. If you share our passion for innovation, we want to meet you.

Job Category: Engineering
Job Subcategory: Design Verification Engineer

We're looking for a Design Verification Engineer to join our Hyderabad/Bangalore team. Does this sound like a good role for you?

Key Qualifications:
• From given design specification, define TB Architecture & develop TB components
• Be a technical contributor in the Verification Tasks – Verilog coding of test-benches, System Verilog, SV Assertions, Test cases, data checks, performing verification tasks such as coverage, debug, regressions using the latest methodologies such as UVM, etc.
• Develop block level test to speed up IP verification
• Work with the verification team to debug and fix RTL issues
• Ability to work/ Prior experience as a Technical Lead is a major plus.

Preferred Experience:
• Typically requires a minimum of 10+ years of IP/SOC Verification experience
• Able to create test-plan & coverage plan with the specification provided
• Knowledge in Serdes and interface technologies such as DDR, MIPI, PCIe, CXL, USB, Ethernet is a plus
• Knowledge in PHY Verification is a plus
• Third party VIP integration & usage is a plus
• Experience in GLS verification & Power-aware simulation is plus
• Experience in Co-Sim/Mixed simulation is plus
• Debugging advanced timing, power, and performance issues
• Chip bring-up, silicon validation, and post-silicon debugging is a plus
• Able to analyze the coverage metrics and improve them with the help of additional test cases in directed environment, at least for small/ medium complexity features of the protocol/product specs
• Familiarity with scripting languages such as shell, Perl, Python etc. is highly desirable
• Exposure to quality processes (QA) in the context of IP design and verification is an added advantage
• Experience with Perforce, Git or similar revision control environment
• Creates deliverables which do not require supervision by a Senior Technical Engineer
• May need to interact with customers to discuss/ understand customers’ specification requirements, if needed
• Managing cross-functional interactions (e.g., with physical design, software, or systems teams)
• Has strong desire to learn and explore new technologies
• Demonstrates good analysis and problem-solving skills
• Be familiar with IP verification flow and signoff flow
• Team building, Innovation, Collaboration

In addition, the candidate should have good communication skills, should be a team player and possess good problem-solving skills and show high levels of initiative.